1. Technical Field
The present disclosure relates to methods for performing an electrical testing of electronic devices.
The present disclosure also relates to systems for performing the electrical testing of electronic devices.
2. Description of the Related Art
At present to perform an electrical wafer sort (EWS) testing of an electronic device to be tested or Device Under Testing (DUT), it is necessary to electrically connect a testing apparatus or tester, such as an Automatic Test Equipment (ATE), with the wafer comprising a plurality of electronic components to be selected. In particular, a probe card is used, comprising at least one probe or more generally a plurality of probes, acting as an interface between the ATE and the wafer. The probe card is a board comprising a printed circuit or Printed Circuit Board (PCB) and several dozens (often even several hundreds) of probes which electrically connect the ATE with most of the electrical terminations or pads of the device to be tested. In fact, the ATE comprises measurement or testing resources which should be connected with all the pads being necessary to perform the testing, and the number of pads for performing the testing can be lower or equal to the number of pads on the device. ATE measurement or testing resources are composed for example of power supplies, signal generators, measurement instruments, computation and processing instruments, etc. By way of example, the attached FIG. 1 shows a device DUT 10, comprising a plurality of pads 11 connected with an ATE, not shown in the figure, by means of a plurality of probes 12 of a probe card, not shown in the figure too.
This kind of method is also adopted for performing, on an electronic device DUT, a final test, for which one or more chips are encapsulated in a single package, which will be connected for example to a plurality of pogo pins of a socket so that an ATE performs the final test thereof.
Similarly, for testing a generic complex electronic system by using an ATE, the resources thereof are connected to the circuits of the electronic system to be tested by means of pads, if it is a question of testing on-wafer chips, or by means of bumps or leads, if the chips are also encapsulated in a package or if the chips are on a wafer comprising the bumps (created for example on pads), or, in general, by means of suitable connectors already comprised in the circuits realized according to the prior art.
The testing of complex on-wafer DUTs performed by using this kind of method is considerably complicated since several testing operations generally should be performed and the wafer should be thus necessarily contacted several times.
Moreover, the use of probes connecting the ATE with the wafer often involves the damaging of the selected device pads, complicating the further device assembly.
Furthermore, performing the testing of several parallel-connected DUT requires the use of probe cards with a very high number of probes, increasing contacting problems and thus of electrical continuity between the probes of the probe card and the DUT pads and also causing problems of electrical yield loss. It should be also said that the number of ATE resources to be used increases according to the number of pads to be contacted on the DUT to be tested and, consequently, the number of DUTs which can be tested in parallel decreases, inevitably increasing testing costs.
A device DUT to be tested can be composed of at least one generic and anyhow complex electronic device or of a set of integrated electronic circuits being encapsulated in a package, or System in Package (SiP), or even of a generic anyhow complex electronic system. Moreover, a device DUT can comprise analog and radio frequency (RF) circuits, digital circuits and one or more different kinds of memories, and various combinations thereof. By way of example, the attached FIG. 2 shows a generic complex device DUT 100 comprising a memory block 103 (for example a Flash memory), an analog circuit block 104, a digital circuit block 105 and a RF circuit block 106. A similar device is generally defined as mixed-signal since it comprises both analog and digital signals and also radio frequency signals.
At present, especially for DUTs being used in the automotive field, performing the testing of devices DUT of such a complex type requires two or more testing operations and, thus, the use of at least two different types of ATE with different temperature conditions. Consequently, the electrical selection process is considerably complicated. In fact, for complex DUT testing, it is necessary to have ATEs of different type and high cost, besides solving production problems due to the analog and RF circuits in the DUT.
For example, as shown in the attached FIG. 3, for performing the testing of the digital block 105 it is necessary to use a specific ATE 107 for the digital testing, which is connected to one part of the DUT resources. For such a testing scanning techniques are usually implemented, i.e., the device is provided with scan cells at the device edge to be able to perform the boundary scanning (for pins) and/or with internal scan cells (for nodes), being series-connected to form scanning chains or scan chains.
For the testing through scan chains suitable Advanced Test Pattern Generator (ATPG) software is often required, generating test patterns at the DUT input. These patterns, called input test vectors, are loaded along the chains in order to stimulate the device internal circuits. In response, output test vectors are generated, being captured by scan cells and then outputted in order to compare them with the expected testing results. This technique thus requires the availability in the ATE of expensive and complex resources, being necessary to store and apply input test vectors and then to compare them with the expected results.
At present, a technique being frequently used and effective for this purpose is scan compression, which reduces by a factor even higher than 10 the number of scan chains to be connected to the digital tester.
Alternatively, boundary scanning techniques are also used, being based on a suitable architecture and design rules being described in the IEEE/ANSI 1149 standard, allowing chips to have a common interface and a testing protocol providing a standard solution.
The digital testing can be performed by using Low Pin Count (LPC) interfaces being useful to reduce the number of pins to be contacted for performing the testing. Nevertheless, the LPC interfaces being used to reduce the number of pads to be contacted are useful only for testing digital DUTs or DUTs being mostly composed of digital circuits. Consequently, in order to allow these LPC testing interfaces to be used it is necessary to insert, in the device, dedicated circuits which disadvantageously occupy a certain device area.
Techniques of the Built In Self Test (BIST) type also are used for performing digital circuit testing, providing that BIST test circuits are integrated within the device and they can test it, given that these circuits add testing resources within the DUT, releasing as much as possible from the ATE. In this sense, for example in the digital circuit case, input test vectors are generated within the DUT, so that the testing occurs inside it and a given circuit block tests itself. In particular, suitable signals are generated on DUT inputs by BIST circuits, for example by means of Linear Feedback Shift Register (LFSR) circuits, while outputs are combined in a datum, called signature. The circuit block to be tested is failure-free if the outputs generate the expected signature. The disadvantage of the structure created by BIST circuits is the unsuitable performance in terms of failure coverage in the case of a generic circuit which can be not completely digital.
Moreover, as shown in the attached FIG. 4, for performing the testing of the memory block 103 a specific ATE 108 for the memory testing is used, by connecting it to a part of the DUT itself. In particular, for testing DUT memory circuits Memory BIST techniques are presently used, or other testing techniques based on the specific kind of memory and on the physics of the memory base element, such as flash memories. In this case too, LPC interfaces are used, reducing the number of pins to be contacted for performing the testing. More in detail, with the flash memory BIST technique, the chip can be inside tested by means of a Core or a microcontroller which can be arranged to perform a firmware code (FW), which is sent from the ATE to the chip by means of a LPC dedicated interface. The advantages of this technique are the possibility to simplify the ATE increasing the testing parallelism and considerably reducing testing costs. Nevertheless, disadvantageously, for performing the testing of non volatile memories (NVM), for example of the flash type, it is necessary to perform two testing flows, since also the retention test of Floating Gate Avalance Metal Oxide Semiconductor (FAMOS) memory cells should be performed.
It is also possible to perform the testing of digital circuits and of memory circuits with a same ATE. In fact, as it is evident from the attached FIG. 5, a specific ATE 109 for the testing of the digital block 105 and of the memory block 103 is used, by connecting one part of the DUT 100, in particular digital and memory blocks, to the resources of ATE 109. In particular, this kind of testing is performed by using some of the above-described techniques.
Similarly, for performing the testing of digital and analog circuits a specific ATE 110 for the testing of mixed-signal circuits is used, or both analog and digital signals, by connecting one part of the DUT 100, in particular digital and analog blocks, to the resources of ATE 110, as shown in the attached FIG. 6. For this kind of mixed-signal testing, dedicated circuits and specific testing methods are usually used, which can sometimes make use of the so-called Intellectual Properties (IPs), according to the specific circuit to be tested. These IPs are composed of particular circuit being able to perform or to enable a testing which is generally but not exclusively of the BIST type. Nevertheless, a disadvantage of this king of testing is that mixed-signal ATEs have a cost which is generally very high and anyhow higher than other kinds of ATE.
For the testing of radio frequency circuits (RF) a specific ATE 111 should be used, by connecting one part of the DUT, in particular radio frequency circuits, to the resources of ATE 111, as shown in the attached FIG. 7. Nevertheless, performing this kind of testing has several problems. For DUTs comprising circuits of the analog and/or RF type, it is very difficult to reduce the number of resources to be contacted, and it is usually necessary to connect the DUT with all ATE resources referring to these circuits. Consequently, ATEs being used are considerably complex and very expensive. Moreover, the presence of analog and RF circuits in the DUT makes the testing difficult because of the several parasitic phenomena in the electrical measurement chain between the DUT and ATE internal instruments.
As shown in the attached FIG. 8, it is possible to perform together the testing of digital, analog and RF circuits, by using a specific ATE 112 for the testing of mixed-signal circuits having therein also specific instruments for RF testing, by connecting one part of the DUT, in particular analog 104, digital 105 and RF 106 blocks, to ATE resources. For performing this kind of testing specific IPs and the above-disclosed techniques are usually used.
Thus, in general, each DUT requires a particular electrical selection or testing process. Thus, finding out a standard testing approach, able to reduce the number of ATEs of different kind to be used for the testing and, consequently, the costs, the complexity of testing flows and of the productive process in general, is a big problem.
A solution for reducing the testing cost of mainly digital chips with some analog circuits is described in the article “Reducing Test Cost Through the use of digital Testers for Analog Tests”, proposed by IBM at the conference IEEE-ITC 2005. In this article, instead of using mixed-signal ATEs having high costs an alternative solution has been chosen, comprising the use of digital ATEs, being available at low cost, adding between the digital ATE and the DUT, a specific interface board, Device Interface Board (DIB), having the resources being necessary for the analog circuit testing. The attached FIG. 9 shows the digital ATE 107, of the type shown in FIG. 3, connected to a DIB board 113 communicating with two devices DUT 200, just acting as an interface between the ATE and the two DUTs. More in detail, the attached FIG. 10 shows the digital ATE 107 connected to the DIB board 113, interfaced with on-wafer DUTs 200 by means of a probe card 114.
The solution being described in the above-mentioned article is effective for mixed-signal DUTs with a low content of analog circuits, while it could be hardly applied to mixed-signal DUTs with a considerable analog part since, in this case, the DIB board would become very complex and expensive. Moreover, the DIB board being described is a dedicated interface to the specific DUT, generally not reusable for other kinds of DUT.